FPGA performance analysis of different forward error correction codes for 5G communication system

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dc.contributor.authorDevrari, Aakanksha
dc.date.accessioned2025-01-27T12:33:44Z
dc.date.available2025-01-27T12:33:44Z
dc.date.issued2024-04
dc.descriptionThesis submitted in partial fulfillment of the requirements for the award of the Degree of Doctor of Philosophy (Electrical & Electronics Engineering)en_US
dc.identifier.citationUnder the guidance of Dr. Adesh Kumar, Professor, Electrical & Electronics Engineering, UPESen_US
dc.identifier.urihttps://dr.ddn.upes.ac.in/handle/123456789/4377
dc.language.isoenen_US
dc.publisherSchool of Advanced Engineering, UPES, Dehradunen_US
dc.subjectThesisen_US
dc.subjectElectrical & Electronics Engineeringen_US
dc.subject5G Wireless Technologyen_US
dc.subjectChannel Coding Techniquesen_US
dc.subjectCommunication Systemen_US
dc.subjectLow-Density Parity Checken_US
dc.subjectField Programmable Gate Arrayen_US
dc.titleFPGA performance analysis of different forward error correction codes for 5G communication systemen_US
dc.typeThesisen_US

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