FPGA performance analysis of different forward error correction codes for 5G communication system

Thumbnail Image

Files

Aakanksha Devrari Thesis SOE.pdf (4.42 MB)

Date

2024-04

Authors

Journal Title

Journal ISSN

Volume Title

Publisher

School of Advanced Engineering, UPES, Dehradun

Abstract

Description

Thesis submitted in partial fulfillment of the requirements for the award of the Degree of Doctor of Philosophy (Electrical & Electronics Engineering)

Keywords

Thesis, Electrical & Electronics Engineering, 5G Wireless Technology, Channel Coding Techniques, Communication System, Low-Density Parity Check, Field Programmable Gate Array

Citation

Under the guidance of Dr. Adesh Kumar, Professor, Electrical & Electronics Engineering, UPES

URI

https://dr.ddn.upes.ac.in/handle/123456789/4377

Collections

Thesis

Endorsement

Review

Supplemented By

Referenced By