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FPGA performance analysis of different forward error correction codes for 5G communication system
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| dc.contributor.author | Devrari, Aakanksha | |
| dc.date.accessioned | 2025-01-27T12:33:44Z | |
| dc.date.available | 2025-01-27T12:33:44Z | |
| dc.date.issued | 2024-04 | |
| dc.identifier.citation | Under the guidance of Dr. Adesh Kumar, Professor, Electrical & Electronics Engineering, UPES | en_US |
| dc.identifier.uri | https://dr.ddn.upes.ac.in//xmlui/handle/123456789/4377 | |
| dc.description | Thesis submitted in partial fulfillment of the requirements for the award of the Degree of Doctor of Philosophy (Electrical & Electronics Engineering) | en_US |
| dc.language.iso | en | en_US |
| dc.publisher | School of Advanced Engineering, UPES, Dehradun | en_US |
| dc.subject | Thesis | en_US |
| dc.subject | Electrical & Electronics Engineering | en_US |
| dc.subject | 5G Wireless Technology | en_US |
| dc.subject | Channel Coding Techniques | en_US |
| dc.subject | Communication System | en_US |
| dc.subject | Low-Density Parity Check | en_US |
| dc.subject | Field Programmable Gate Array | en_US |
| dc.title | FPGA performance analysis of different forward error correction codes for 5G communication system | en_US |
| dc.type | Thesis | en_US |
